XRT79L71_10 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71_10' PDF : 609 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Figure 6 presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals, during
an "Intel-Asynchronous" Mode Read Operation.
FIGURE 6. BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS DURING AN "INTEL-ASYNCHRONOUS" READ
OPERATION.
Microprocessor places “target”
Address value on A[14:0]
Microprocessor Interface latches contents on
A[14:0] upon falling edge of ALE
ALE/AS
A[14:0]
Address of Target Register
CS*
D[7:0]
Not Valid
Valid
RD*/DS*
WR*/R/W*
RDY*/DTACK*
Address Decoding
Circuitry asserts
CS*
Read Operation begins
Here
RDY* toggles “low” to indicate
That valid data can be read from
D[7:0]
Read Operation is
Terminated Here
RDY* toggle “high” after
Completion of Read
Operation
2.1.2 The Intel-Asynchronous Write Cycle
If the Microprocessor Interface (of the XRT79L71) has been configured to operate in the Intel-Asynchronous
Mode, then the Microprocessor should do all of the following, anytime it wishes to write a byte of data into a
register or some location within the Transmit LAPD Message buffer, the Transmit Cell Insertion Memory or the
Receive Cell Insertion Memory (within the XRT79L71), it should do the following.
1. Place the address of the "target" register or buffer location (within the XRT79L71) on the Address Bus
input pins, A[14:0].
2. While the µC/µP is placing the address value on the Address Bus, the Address Decoding circuitry (within
the user's system) should assert the CS (Chip Select) input pin of the XRT79L71, by toggling it "low".
This action enables further communication between the µC/µP and the XRT79L71 Microprocessor
Interface.
3. Toggle the ALE/AS (Address Latch Enable) input pin "high". This step enables the "Address Bus" input
drivers, within the Microprocessor Interface block of the XRT79L71.
4. After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Setup"
time) the µC/µP should toggle the ALE/AS input pin "low". This step causes the XRT79L71 to "latch" the
contents of the "Address Bus" into its internal circuitry. At this point, the address of the register or buffer
locations (within the XRT79L71) has now been selected.
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