XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
NOTE: The GIE bit in the global register 0x80h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 28: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-7 (0X05H-0X75H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D1
RLOS Receiver Loss of Signal
RO
0
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x04h and GIE is set to "1" in the global
register 0x80h.
0 = No Alarm
1 = An RLOS condition is present
D0
QRPD Quasi Random Pattern Detection
RO
0
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0x04h and GIE is set to "1" in
the global register 0x80h.
0 = No Alarm
1 = A QRP is detected
TABLE 29: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION
CHANNEL 0-7 (0X06H-0X76H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used.
D6
DMOIS Digital Monitor Output Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS FIFO Limit Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV/OFIS Line Code Violation / Overflow Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved This Register Bit is Not Used.
D2
AISDIS Alarm Indication Signal Status
0 = No change
1 = Change in status occurred
RUR
0
59