XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
REV. 1.0.7
D1
D0
XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 39: MICROPROCESSOR REGISTER 0X81H, BIT DESCRIPTION
EXLOS Extended LOS: Writing a “1” to this bit extends the number of R/W
0
zeros at the receive input of each channel before RLOS is
declared to 4096 bits. Writing a “0” reverts to the normal mode
(175+75 bits for T1 and 32 bits for E1).
ICT
In-Circuit-Testing: Writing a “1” to this bit configures all the
R/W
0
output pins of the chip in high impedance mode for In-Circuit-
Testing. Setting the ICT bit to “1” is equivalent to connecting
the Hardware ICT pin 88 to ground.
BIT
D7
D6
D[5:0]
TABLE 40: MICROPROCESSOR REGISTER 0X82H BIT DESCRIPTION
GLOBAL REGISTER (0X82H)
NAME
FUNCTION
Register
Type
TxONCNTL Transmit On Control
R/W
0 = Control of receive termination is set;
if in Hardware mode, by RxTSEL Pins
If in Host mode by the RxTsel bit
0 = Control of Transmitter is set ;
if Hardware mode, by TxON pin
if Host mode, by TxON bit
1 = Control of transmitter on, is determined by the individual chan-
nel TxOn bits
TERCNTL Receive Termination Select Control
R/W
This bit sets the LIU to control the RxTSEL function with either the
individual channel register bit or the global hardware pin.
0 = Control of the receive termination is set tby Hardware-Host bit
or Hardware pin and individual software
1 = Control of the receive termination is set to the hardware pin
Reserved These Register Bits are Not Used
Default
Value
(HW reset)
0
0
66
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