XRT83SL34 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL34' PDF : 80 Pages View PDF
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
ARBITRARY PULSE GENERATORFOR T1 AND E1
The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit
binary word by programming the appropriate channel register. This allows the system designer to set the
overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is
set to “1”, the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set
to “0”, the segment will move in a negative direction relative to a flat line condition. A pulse with numbered
segments is shown in Figure 9.
FIGURE 9. ARBITRARY PULSE SEGMENT ASSIGNMENT
Segment
1
2
3
4
5
6
7
8
Register
0xn8
0xn9
0xna
0xnb
0xnc
0xnd
0xne
0xnf
1
2
3
4
8
7
6
5
NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern
to the line.
TRANSMITTER
Each individual transmitter channel can be turned on or off in both Hardware and Host modes.
DIGITAL DATA FORMAT
Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature
is available under both Hardware and Host control modes, on a global basis. The dual or single-rail data
format is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host
mode. In single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins
respectively. In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES
function. With TNEG_n/CODES_n tied “Low”, HDB3 or B8ZS encoding and decoding are enabled for E1 and
T1 modes respectively. With TNEG_n/CODES_n tied “High”, the AMI coding scheme is selected. In both dual
or single-rail modes of operations, the transmitter converts digital input data to a bipolar format before being
transmitted to the line.
TRANSMIT CLOCK (TCLK) SAMPLING EDGE
Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83SL34 under the
synchronization of TCLK_n. With a “0” written to the TCLKE interface bit, or by pulling the TCLKE pin “Low”,
input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a “1” written to TCLKE
interface bit, or by connecting the TCLKE pin “High”.
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