XRT83SL34 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL34' PDF : 80 Pages View PDF
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.0.8
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS
EQC4
EQC3
EQC2
EQC1
EQC0
E1/T1 MODE & RECEIVE
SENSITIVITY
TRANSMIT LBO
CABLE
CODING
1
1
1
1
0
E1 Gain Mode
1
1
1
1
1
E1 Gain Mode
ITU G.703
ITU G.703
75Ω Coax
120Ω TP
HDB3
HDB3
TRANSMIT AND RECEIVE TERMINATIONS
The XRT83SL34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide
applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the
use of existing components and/or designs.
RECEIVER (CHANNELS 0 - 3)
INTERNAL RECEIVE TERMINATION MODE
In Hardware mode, RXTSEL (Pin 83) can be tied “High” to select internal termination mode for all receive
channels or tied “Low” to select external termination mode. Individual channel control can only be done in Host
mode. By default the XRT83SL34 is set for external termination mode at power up or at Hardware reset.
TABLE 6: RECEIVE TERMINATION CONTROL
RXTSEL
RX TERMINATION
0
EXTERNAL
1
INTERNAL
In Host mode, bit 7 in the appropriate channel register, (Table 20, “Microprocessor Register #1, Bit
Description,” on page 46), is set “High” to select the internal termination mode for that specific receive channel.
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