XRT83SL34 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL34' PDF : 80 Pages View PDF
XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.0.8
PRELIMINARY
FIGURE 11. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE
TPOS
TNEG
TCLK
TX
Line Driver
RPOS
RNEG
RCLK
RX
Equilizer
Channel _n
R int
TTIP
0.68µ F
1
T1 5
TRING
R int
RTIP
R int
RRING
4
8
1:2
5
T2 1
8
4
1:1
TTIP
75 Ω , 100 Ω
110 Ω or 120 Ω
TRING
RTIP
75 Ω , 100 Ω
110 Ω or 120 Ω
RRING
If the internal termination mode (RXTSEL = “1”) is selected, the effective impedance for E1, T1 or J1 can be
achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7.
NOTE: In Hardware mode, pins RXRES[1:0] control all channels.
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