XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
REV. 1.0.1
TRANSMIT SERIAL DATA INPUT
(Framer Channel Number indicated by _n)
XRT84L38
OCTAL T1/E1/J1 FRAMER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
TxTSClk_0
TxTSClk_1
TxTSClk_2
TxTSClk_3
TxTSClk_4
TxTSClk_5
TxTSClk_6
TxTSClk_7
D10
B14
C21
D25
AB25
AE20
AE13
AC5
O Transmit Channel Clock Output Signal—Framer_n:
This pin indicates the boundary of each time slot of an outbound DS1/E1
frame.
DS1 Mode:
Each of these output pins are a 192kHz clock output which pulses "High"
whenever the Transmit Payload Data Input Interface block accepts the LSB of
each of the 24 time slots, within the DS1 data stream, being processed via
Framer _n. The Terminal Equipment should use this clock signal to sample the
TxTSb0_n through TxTSb4_n output signals and identify the time-slot being
processed via the "Transmit Section" of each Framer_n.
If TxTSb1_n pin is configured as TxFrTD_n to input fractional DS1 payload
data into Framer_n, the TxTSClk_n pin can be configured to function as one of
the following:
The pin will output gaped fractional DS1 clock that can be used by terminal
equipment to clock out fractional DS1 payload data at rising edge of the clock.
Framer_n will then input fractional DS1 payload data using falling edge of the
clock.Otherwise, this pin will be a clock enable signal to Transmit fractional
DS1 Input (TxFrTD_n) if Framer_n is configured accordingly. In this mode,
fractional DS1 payload data is clocked into the chip using un-gaped
TxSerClk_n.
E1 Mode:
Each of these output pins are a 256kHz clock output which pulses "High"
whenever the Transmit Payload Data Input Interface block accepts the LSB of
each of the 32 time slots, within the E1 data stream, being processed via
Framer _n. The Terminal Equipment should use this clock signal to sample the
TxTSb0_n through TxTSb4_n output signals, and identify the time-slot being
processed via the "Transmit Section" of each Framer_n.
If TxTSb1_n pin is configured as TxFrTD_n to input fractional E1 payload data
into Framer_n, the TxTSClk_n pin can be configured to function as one of the
following: The pin will output gaped fractional E1 clock that can be used by ter-
minal equipment to clock out fractional E1 payload data at rising edge of the
clock. Framer_n will then input fractional E1 payload data using falling edge of
the clock.Otherwise, this pin will be a clock enable signal to Transmit fractional
E1 Input (TxFrTD_n) if Framer_n is configured accordingly. In this mode, frac-
tional E1 payload data is clocked into the chip using un-gaped TxSerClk_n.
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