XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
RECEIVE SERIAL DATA OUTPUT
(Framer Channel Number indicated by _n)
SIGNAL NAME
RxSync_0
RxSync_1
RxSync_2
RxSync_3
RxSync_4
RxSync_5
RxSync_6
RxSync_7
RxMSync_0
RxMSync_1
RxMSync_2
RxMSync_3
RxMSync_4
RxMSync_5
RxMSync_6
RxMSync_7
PIN #
A3
B11
B16
C24
V26
AC22
AD14
AE7
B3
C9
A19
A26
V25
AD24
AF13
AC8
TYPE
DESCRIPTION
I or O
Single Frame Sync Pulse Input/Output pin—Receive Framer_n:
This pin is configured to be an Input if the Slip Buffer associated with Framer_n is
enabled. Conversely, this pin will be configured to be an Output if the Slip-
Buffer is by-passed.
DS1 Mode:
When pin is configured to be an Input
If this pin is configured to be an input, then the user must pulse this pin "High"
for one period of RxSerClk_n, when the Receive payload data output Interface
(of Framer_n) is processing the first bit (F-bit) of an inbound DS1 frame.
NOTE: It is imperative that the RxSync_n input signal be synchronized with the
RxSerClk_n input signal.
When pin is configured to be an Output
If this pin is configured to be an output, then it will pulse "High", for one period of
RxSerClk_n, when the Receive payload data output Interface (of Framer_n) is
processing the first bit (F-bit) of an inbound DS1 frame.
E1 Mode:
When pin is configured to be an Input
If this pin is configured to be an input, then this pin must be pulsed "High" for
one period of RxSerClk_n, when the Receive E1 Serial (or Overhead) Output
Interface, outputs the International bit (Si) of an inbound E1 frame.
NOTE: It is imperative that the RxSync_n input signal be synchronized with the
RxSerClk_n input signal.
When pin is configured to be an Output
If this pin is configured to be an output, then it will pulse "High" for one period of
RxSerClk_n, when the Receive E1 Serial (or Overhead) output Interface outputs
the last bit, in an inbound E1 frame.
O Multiframe Sync Pulse Output--Receive Framer_n:
This DS1-only signal will pulse "High" for one period of RxSerClk_n, the instant
that the Receive payload data Interface (of Framer_n) is processing the first bit
of a DS1 Multi-frame.
RxCRCMSync_0
RxCRCMSync_1
RxCRCMSync_2
RxCRCMSync_3
RxCRCMSync_4
RxCRCMSync_5
RxCRCMSync_6
RxCRCMSync_7
B3
C9
A19
A26
V25
AD24
AF13
AC8
O Receive "CRC Multiframe" Sync Output signal-Framer_n:
This E1-only signal pulses "High" for one period of RxSerClk_n whenever the
Receive E1 Output Interface of Framer_n outputs the first bit, within a given
"CRC Multiframe".
NOTE: This output pin is inactive if CRC Multiframe Alignment is disabled.
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