XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
REV. 1.0.1
OVERHEAD INTERFACE
(Framer Channel Number indicated by _n)
XRT84L38
OCTAL T1/E1/J1 FRAMER
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
RxOH_0
RxOH_1
RxOH_2
RxOH_3
RxOH_4
RxOH_5
RxOH_6
RxOH_7
C7
B10
C19
B26
W25
AC20
AF18
AC11
O Receive Overhead Output—Framer_n:
This pin, along with RxOHClk_n functions as the Receive Overhead Output
Interface for Framer_n.
DS1 Mode:
This pin unconditionally outputs the contents of the Facility Data Link Bit in ESF
framing mode, Fs bit in the SLC96 and N framing mode, and R bit in T1DM
framing mode.
NOTE: This output pin is active even if the Receive HDLC Controller (within
Framer_n) is active.
E1 mode:
This pin unconditionally outputs the contents of the National Bits (the "Sa4"
through the "Sa8" bits). If Framer_n has been configured to interpret the
National bits of the incoming E1 frames as carrying "Data Link" information; then
the Receive Overhead Output Interface will provide a clock pulse (via the
RxOHClk_n output pin) for each "Sa" bit carrying Data Link information.
NOTE: This output pin is active even if the Receive HDLC Controller (within
Framer_n) is active.
RxOHClk_0
RxOHClk_1
RxOHClk_2
RxOHClk_3
RxOHClk_4
RxOHClk_5
RxOHClk_6
RxOHClk_7
C5
B12
D19
B25
V23
AE21
AD17
AD10
O Receive OH Serial Clock Output Signal—Framer_n:
This pin, along with RxOH_n functions as the Receive Overhead Output Inter-
face for Framer_n.
DS1 Mode:
This pin outputs a clock edge corresponding to each Facility Data Link Bit in
ESF framing mode, Fs bit in the SLC96 and N framing mode, and R bit in T1DM
framing mode, which carries Data Link information.
NOTES:
1. Depending on the configurations of Framer_n, the clock frequency in
ESF framing mode can be 2KHz or 4KHz.
2. This output pin is inactive if the Receive HDLC Controller (within
Framer_n) has been enabled.
E1 mode:
This pin outputs a clock edge corresponding to each National Bit that is carrying
"Data Link" information.
NOTE: This output pin is inactive if the Receive HDLC Controller (within
Framer_n) has been enabled.
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