XRT84L38 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT84L38' PDF : 453 Pages View PDF
XRT84L38
OCTAL T1/E1/J1 FRAMER
RECEIVE SERIAL DATA OUTPUT
(Framer Channel Number indicated by _n)
REV. 1.0.1
SIGNAL NAME
PIN #
TYPE
DESCRIPTION
RxSerClk_0
RxSerClk_1
RxSerClk_2
RxSerClk_3
RxSerClk_4
RxSerClk_5
RxSerClk_6
RxSerClk_7
B2
B9
A17
E23
U24
AF25
AD15
AD7
I or O Receive Serial Clock Signal—Receive Framer_n: (Continued)
Receive Back-plane Interface-Multiplexed at 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 01 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
Receive Back-plane Interface-HMVIP, 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 10 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
Receive Back-plane Interface-H.100, 16.384 MHz Clock Mode
If RxMUXEN = 1 and RxIMODE[1:0] = 11 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting multiplexed data at a
rate of 16.384 Mbit/s. RxSerClk_0 and RxSerClk_4 signals will be Input clock
signals running at 16.384 MHz. RxSerClk_1, 2, 3 and RxSerClk_5, 6, 7 signals
are not required. Received DS1 Payload data of Channel 0, 1, 2 and 3 are mul-
tiplexed and latched out from Receive back-plane interface using clock edge of
RxSerClk_0 via RxSer_0 output pin. Receive DS1 Payload data of Channel 4,
5, 6 and 7 are multiplexed and latched out from Receive back-plane interface
using clock edge of RxSerClk_4 via RxSer_4 output pin.
E1 Mode:
Receive Back-plane Interface-2.048 MHz (XRT84V24 Compatible) Clock
Mode
If RxMUXEN = 0 and RxIMODE[1:0] = 00 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting data at a XRT84V24
compatible rate of 2.048 Mbit/s. This pin is configured to be an Input if the Slip
Buffer associated with Framer_n is enabled. Conversely, this pin will be config-
ured to be an Output if the "Slip-Buffer" is "by-passed".
Receive Back-plane Interface-2.048 MHz Clock Mode
If RxMUXEN = 0 and RxIMODE[1:0] = 01 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting data at a rate of 2.048
Mbit/s. The RxSerClk_n signal will be an Input clock signal running at 2.048
MHz.
Receive Back-plane Interface-4.096 MHz Clock Mode
If RxMUXEN = 0 and RxIMODE[1:0] = 10 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting data at a rate of 4.096
Mbit/s. The RxSerClk_n signal will be an Input clock signal running at 4.096
MHz.
Receive Back-plane Interface-8.192 MHz Clock Mode
If RxMUXEN = 0 and RxIMODE[1:0] = 11 in Receive interface control register,
Receive back-plane interface of Framer_n is presenting data at a rate of 8.192
Mbit/s. The RxSerClk_n signal will be an Input clock signal running at 8.192
MHz.
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