XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
xr
REV. P1.1.0
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
3.2 Transmit Parallel Data Input Timing
When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in
Figure 10 and Table 6.
FIGURE 10. TRANSMIT PARALLEL INPUT TIMING
TXPCLKOP/N
tTXPCLKO
TXPCLKIP/N
TXDI[15:0]P/N
tTXDI_SU
tTXPCLKI
tTXDI_HD
TABLE 6: TRANSMIT PARALLEL DATA AND CLOCK INPUT TIMING SPECIFICATION
SYMBOL
tTXPCLKI
tTXPCLKI
tTXDI_SU
tTXDI_HD
TXDUTY
PARAMETER
Transmit parallel clock input period (622.08 MHz non-FEC rate)
Transmit parallel clock input period (666.51 MHz FEC rate)
TXPCLKIP/N "High" to data setup time
TXPCLKIP/N "High" to data hold time
TXPCLKIP/N Duty Cycle
MIN
TYP
MAX UNITS
1608
ps
1500
ps
300
ps
300
ps
40
60
%
TABLE 7: TRANSMIT PARALLEL CLOCK OUTPUT TIMING SPECIFICATION
SYMBOL
tTXPCLKO
tTXPCLKO
TXDUTY
PARAMETER
Transmit parallel clock output period (622.08 MHz non-FEC rate)
Transmit parallel clock output period (666.51 MHz FEC rate)
TXPCLKOP/N Duty Cycle
MIN
TYP
MAX UNITS
1608
ps
1500
ps
45
55
%
3.3 Transmit FIFO
The parallel interface also includes a 4x9 FIFO that can be used to eliminate difficult timing issues between the
input transmit clock and the clock derived from the CMU. The use of the FIFO permits the system to tolerate an
arbitrary amount of delay and jitter between TXPCLKOP/N and TXPCLKIP/N. The FIFO can be initialized
when FIFO_RST is asserted and held "High" for 2 cycles of the TXPCLKOP/N clock. When the FIFO_RST is
de-asserted, it will take 8 to 10 TXPCLKOP/N cycles for the FIFO to flush out. Once the FIFO is centered, the
delay between TXPCLKOP/N and TXPCLKIP/N can decrease or increase up to two periods of the low-speed
clock. Should the delay exceed this amount, the read and write pointers will point to the same Nibble in the
FIFO resulting in a loss of transmitted data (FIFO overflow). In the event of a FIFO overflow, the FIFO control
logic will initiate an OVERFLOW signal that can be used by an external controller to issue a FIFO RESET
signal. The device under the control of the FIFO_AUTORST pin can automatically recover from an overflow
condition. When the FIFO_AUTORST input is set to a "High" level, once an overflow condition is detected, the
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