XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that
is applied to the REFCLKP/N inputs. In this case, the LOOPTM_NOJA pin should be set "Low", the
VCXO_SEL set "High", and the LOOPTM_JA pin set "Low". In this configuration, the REFCLKP/N signal is
used as the reference to the de-jitter PLL and the de-jittered output of the phase locked VCXO is used as the
timing reference to the CMU. Table 9 provides configuration for selecting the loop timing and reference de-jitter
modes.
TABLE 9: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS
VCXO_SEL
LOOPTM_JA
LOOPTM_NOJA
ACTION
0
0
0
Normal mode
0
0
1
Loop timing without de-jitter VCXO
1
0
0
REFCLKP/N reference de-jitter VCXO
1
1
0
Loop timing with de-jitter VCXO
FIGURE 13. LOOP TIMING MODE USING AN EXTERNAL CLEANUP VCXO
VCXO
LOOPTM_NOJA
LOOPTM_JA
VCXO_SEL
REFCLKP
REFCLKN
VCXO_INP
VCXO_INN
LOCKDET_CMU
VCXO_LOCK
ALTFREQSEL
~
Loop Filter
0
Phase
Charge
1
Detect
Pump
CPOUT
0
0
1
1
2.488/2.666GHz
CMU
PISO
2.488/2.666GHz
Retimer
TXOP
TXON
Div by 16
or 32
XRT91L80
Clk
CDR
Data
RXIP
RXIN
~
22
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