XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
xr
REV. P1.1.0
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK
The serial microprocessor uses a standard 3-pin serial port with CS, SCLK, and SDI for programming the
transceiver. Optional pins such as SDO, INT, and RESET allow the ability to read back contents of the
registers, monitor the transceiver via an interrupt pin, and reset the transceiver to its default configuration by
pulling reset "Low" for more than 10ms. A simplified block diagram of the Serial Microprocessor is shown in
Figure 24.
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE
CS
SCLK
SDO
INT
SDI
Serial
Microprocessor
Interface
HW/Host
RESET
5.1 SERIAL TIMING INFORMATION
The serial port requires 16 bits of data applied to the SDI (Serial Data Input) pin. The Serial Microprocessor
samples SDI on the rising edge of SCLK (Serial Clock Input). The data is not latched into the device until all 16
bits of serial data have been sampled. A timing diagram of the Serial Microprocessor is shown in Figure 25.
FIGURE 25. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE
CS
SCLK
SDI
SDO
25nS
50nS
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
R/W A0 A1 A2 A3 A4 A5 X D0 D1 D2 D3 D4 D5 D6 D7
High-Z
D0 D1 D2 D3 D4 D5 D6 D7
High-Z
NOTE: The serial microprocessor interface does NOT support "burst write" or "burst read" operations. Chip Select (active
"Low") must be de-asserted at the end of every single write or single read operation.
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