XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
TABLE 14: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
BIT
NAME
CONFIGURATION 0 CONTROL REGISTER (0X03H)
FUNCTION
Register
Type
Default
Value
(HW reset)
D4
LOOPBW CMU Loop Band Width Select
R/W
0
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band. Use Wide Band for
clean reference signals and Narrow Band for noisy references.
"0" = Wide Band (4x)
"1" = Narrow Band (1x)
D3
VCXO_SEL VCXO De-Jitter Select
This bit selects either the normal REFCLKP/N or the de-jitter
VCXO_INP/N as a reference clock.
"0" = Normal REFCLKP/N Mode
"1" = De-Jitter VCXO Mode
R/W
0
D2 TXCLKO16DIS Auxiliary Clock Disable
This bit is used to control the activity of the auxiliary clock.
"0" = TXCLKO16P/N Enabled
"1" = TXCLKO16P/N Disabled
R/W
0
D1
FIFO_
Automatic FIFO Overflow Reset
R/W
0
AUTORST
If this bit is set to "1", the STS-48/STM-16 transceiver will automat-
ically flush the FIFO upon an overflow condition. Upon power-up,
the FIFO should be manually reset by setting FIFO_RST to "1" for
a minimum of 2 TXPCLKOP/N cycles.
"0" = Manual FIFO reset required for Overflow Conditions
"1" = Automatically resets FIFO upon Overflow Detection
D0
FIFO_RST Manual FIFO Reset
R/W
0
FIFORST should be set to "1" for a minimum of 2 TXPCLKOP/N
cycles after powering up and during manual FIFO reset. After the
FIFO_RST bit is returned "Low," it will take 8 to 10 TXPCLKOP/N
cycles for the FIFO to flush out. Upon an interrupt indication that
the FIFO has an overflow condition, this bit is used to reset or flush
out the FIFO.
"0" = Normal Operation
"1" = Manual FIFO Reset
NOTE: To automatically reset the FIFO, see the FIFO_AUTORST
bit.
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