XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
xr
REV. P1.1.0
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE 15: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
CONFIGURATION 1 CONTROL REGISTER (0X04H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
X
X
D6
POLARITY Polarity for SDEXT Input
R/W
0
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
D5 LOOPTM_JA Loop Timing With Jitter Attenuation
R/W
0
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Loop timing with de-jitter PLL Activated
D4
LOOPTM_ Loop Timing With No Jitter Attenuation
R/W
0
NOJA
When the loop timing mode is activated, the external local refer-
ence clock input to the CMU is replaced with the 1/16th or 1/32nd
of the high-speed recovered receive clock coming from the CDR.
"0" = Disabled
"1" = Loop timing Activated
D3
LOSDMUTE Parallel Receive Data Output Mute Upon LOSD
R/W
0
If this bit is set to "1", the receive data output will automatically be
forced to a logic state of "0" when an LOSD condition occurs.
"0" = Disabled
"1" = Mute RXDO[3:0]P/N Data Upon LOSD Condition
D2
DISRD
Parallel Receive Data Output Disable
R/W
0
This bit is used to disable the RXDO[3:0]P/N parallel receive data
output bus asynchronously.
"0" = Normal Mode
"1" = Forces RXDO[3:0]P/N to a logic state "0"
D1
Reserved Reserved - Set to 0
R/W
0
D0
VCXOLKEN De-Jitter PLL Lock Detect Enable
R/W
0
This bit enables the VCXO_INP/N lock detect circuit to be active.
"0" = VCXO Lock Detect Disabled
"1" = VCXO Lock Detect Enabled
TABLE 16: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
DIAGNOSTIC CONTROL REGISTER (0X05H)
BIT
NAME
FUNCTION
D7
Reserved This Register Bit is Not Used
D6
Reserved This Register Bit is Not Used
Register
Type
X
X
Default
Value
(HW reset)
X
X
35
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