XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
xr
REV. P1.1.0
PRELIMINARY
XRT91L80
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
6.0 REGISTER MAP AND BIT DESCRIPTIONS
TABLE 10: MICROPROCESSOR REGISTER MAP
REG ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Channel 0 Control Register (0x00h - 0x05h)
0
0x00
1
0x01
2
0x02
3
0x03
4
0x04
5
0x05
0x06 - 0x3D
R/W
RUR
RO
R/W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved ALTFREQSEL Reserved
R/W Reserved
R/W Reserved
R/W Reserved
POLARITY
Reserved
LOOPTM_
JA
Reserved
VCXOIE
VCXOIS
VCXOD
LOOPBW
LOOPTM_
NOJA
Reserved
LOSIE
CDRIE
CMUIE
FIFOIE
LOSIS
CDRIS
CMUIS
FIFOIS
LOSD
CDRD
CMUD
FIFOD
VCXO_SEL TXCLK016DIS FIFO_AUTO-
RST
FIFORST
LOSDMUTE
DISRD
Reserved VCXOLKEN
Reserved
DLOOP
RLOOPS
RLOOPP
62 0x3E RO Device ID (See Bit Description)
63 0x3F RO Revision ID (See Bit Description)
TABLE 11: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION
INTERRUPT ENABLE CONTROL REGISTER (0X00H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
X
X
D6
Reserved This Register Bit is Not Used
X
X
D5
Reserved This Register Bit is Not Used
X
X
D4
VCXOIE Voltage Controlled External Oscillator Lock Interrupt Enable
R/W
0
"0" = Masks the VCXO Lock interrupt generation
"1" = Enables Interrupt generation
NOTE: VCXOLKEN must be enabled for this bit to have functional
meaning.
D3
LOSIE Loss of Signal Interrupt Enable
"0" = Masks the LOS interrupt generation
"1" = Enables Interrupt generation
R/W
0
D2
CDRIE Clock and Data Recovery Lock Interrupt Enable
"0" = Masks the CDR Lock interrupt generation
"1" = Enables Interrupt generation
R/W
0
D1
CMUIE Clock Multiplier Unit Lock Interrupt Enable
"0" = Masks the CMU Lock interrupt generation
"1" = Enables Interrupt generation
R/W
0
D0
FIFOIE FIFO Overflow Interrupt Enable
"0" = Masks the FIFO Overflow interrupt generation
"1" = Enables Interrupt generation
R/W
0
31
Share Link: 
