XRT91L80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L80' PDF : 45 Pages View PDF
XRT91L80
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
xr
REV. P1.1.0
device will set the OVERFLOW pin to a "High" level and will automatically reset and center the FIFO. Figure 11
provides a detailed overview of the transmit FIFO in a system interface.
FIGURE 11. TRANSMIT FIFO AND SYSTEM INTERFACE
Upstream Device
AUTORST
OVERFLOW
RESET
TXPCLKIP/N
XRT91L80
delay
4 x 9 FIFO
Write Pointer
TXDI[3:0]P/N
4
TXPCLKOP/N
REFCLKP/N
Read Pointer
2.488/2.666 GHz PLL
CMU
4
FIFO Control
Div by 4
3.4 FIFO Calibration Upon Power Up
It is required that the FIFO_RST pin be pulled "High" for 2 TXPCLKOP/N cycles to flush out the FIFO after the
device is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually
reset the FIFO. However, the STS-48/STM-16 transceiver has an automatic reset pin that will allow the FIFO to
automatically reset upon an Overflow condition. FIFO_AUTORST should be pulled "High" to enable the
automatic FIFO reset function.
3.5 Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 622.08/666.51 MHz parallel data input to 2.488/2.666 Gbps serial data output
which can interface to an optical module. The PISO bit interleaves parallel data input into a serial bit stream
taking the first bit from TXDI3P/N, then the first bit from TXDI2P/N, and so on as shown in Figure 12.
FIGURE 12. SIMPLIFIED BLOCK DIAGRAM OF PISO
4-bit Parallel LVDS Data Input
TXDI0P/N b07 b06 b05 b04 b03 b02 b01 b00
TXDI1P/N b17 b16 b15 b14 b13 b12 b11 b10
TXDI2P/N b27 b26 b25 b24 b23 b22 b21 b20
time (0)
2.488/2.666 Gbps
b30 b20 b10 b00 b31 b21 b11 b01 b32 b22 b12 b02 b33 b23 b13 b03
TXDI3P/N b37 b36 b35 b34 b33 b32 b31 b30
TXPCLKIP/N
622.08/666.51 MHz
TXOP/N
20
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