XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
PRELIMINARY
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
2.5 Receive Parallel Output Interface
The 4-bit LVDS 622/666MHz parallel output data of the receive path is used to interface to a SONET Framer/
ASIC synchronized to the recovered clock. A simplified block diagram is shown in Figure X.
FIGURE 5. RECEIVE PARALLEL OUTPUT INTERFACE BLOCK
RXDO0P/N
RXDO1P/N
RXDO2P/N
RXDO3P/N
RXCLKP/N
XRT91L81 OC48
Transceiver
SONET Framer/ASIC
2.6 Receive Parallel Output Data Timing
The receive parallel output data from the OC-48 receiver will adhere to the setup and hold times shown in
Figure 6 and Table 3.
FIGURE 6. RECEIVE PARALLEL OUTPUT TIMING
RxCLKP/N
RxDO[3:0]P/N
RXINV
RXDEL
TABLE 3: RECEIVE PARALLEL OUTPUT DATA TIMING SPECIFICATIONS
Test Conditions: TA = 25°C, VDD = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN.
RXINV RxCLKP/N "High" to data invalid window
RXDEL RxCLKP/N "High" to data delay
45
RXDTY RxCLKP/N Duty Cycle
TYP.
50
MAX. UNITS
200
pS
55
%
%
CONDITIONS
2.7 Disable Receive Output Data Upon LOS
The Receiver outputs can automatically be pulled "Low" during a LOS condition to prevent data chattering. By
pulling DISRD "High", the Receiver outputs will pull "Low" any time a LOS condition occurs.
2.8 Tri-State Receive Output Data
Unlike DISRD, TRIRXD is used to tri-state the Receiver outputs regardless of the input data stream. By pulling
TRIRXD "High", the Receiver outputs will automically tri-state.
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