XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
3.5 Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 622/666MHz parallel input data to 2.488/2.666GHz serial output data which can
interface to an optical module. The PISO bit interleaves parallel input data into a serial bit stream taking the
first bit from TXDI3P/N, then the first bit from TXDI2P/N, and so on as shown in Figure 9.
FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF PISO
4-bit Parallel LVDS Input Data
TXDI0P/N b07 b06 b05 b04 b03 b02 b01 b00
TXDI1P/N b17 b16 b15 b14 b13 b12 b11 b10
TXDI2P/N b27 b26 b25 b24 b23 b22 b21 b20
TXDI3P/N b37 b36 b35 b34 b33 b32 b31 b30
TXCLKIP/N
622MHz
time (0)
2.488GHz
b30 b20 b10 b00 b31 b21 b11 b01 b32 b22 b12 b02 b33 b23 b13 b03
TXOP/N
3.6 Clock Multiplier Unit (CMU) and Re-Timer
The high-speed serial clock synthesized by the CMU is divided by 4, and the TXPCLKOP/N clock is presented
to an upstream device. The upstream device should use TXPCLKOP/N as its timing source. The Upstream
device then generates the TXCLKIP/N clock that is phase aligned with the transmit data and provides it to the
parallel interface of the transmitter. The data must meet setup and hold times with respect to TXCLKIP/N. The
XRT91L81 will latch TXDI[3:0]P/N on the falling edge of TXCLKIP/N. The clock synthesizer uses a PLL to lock
to the differential input reference clock. It can also be driven by an optional external VCXO for loop timed or
local reference de-jitter applications. As an example the REFCLKP/N input can accept a clock from a LVPECL
crystal oscillator that has a frequency accuracy better than 20ppm in order for the TXCLKOP/N frequency to
have the accuracy required for SONET systems. The other input, VCXO_INP/N can be connected to the
output of a VCXO that can be configured to clean up the recovered received clock in loop timing mode before
being applied to the input of the transmit CMU as a reference clock. In addition, the internal phase/frequency
detector and charge pump, combined with an external VCXO can alternately be used as a jitter attenuator to
de-jitter a noisy system reference clock prior to it being used to time the CMU. Figure 10 provides a detailed
overview of the transmit FIFO in a system interface.
18
Share Link: 
