XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
3.0 TRANSMIT SECTION
The transmit section of the XRT91L81 accepts 4-bit parallel LVDS data and converts it to serial CML output
data intented to interface to an optical module. It consists of a 4-bit parallel LVDS interface, a 4x9 FIFO,
Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current Mode Logic (CML) differential line driver,
and Loop Timing modes. The CML serial output data rate is 2.488/2.666Gbps for OC-48 applications. The high
frequency serial clock is synthesized by a PLL, which uses a low frequency clock as its input reference. In
order to synchronize the data transfer process, the synthesized 2.488/2.666GHz serial output clock is divided
by four and the 622/666MHz clock is presented to the upstream device to be used as its timing source.
3.1 Transmit Parallel Interface
The parallel data from an upstream device is presented to the XRT91L81 through a 4-bit LVDS parallel bus
interface TXDI[3:0]. The data is latched into a parallel input register on the rising edge of TXPCLKIP/N. If the
SONET Framer/ASIC is synchronized to the same timing source as the XRT91L81, the transmit input data and
clock can directly interface to the OC-48 transceiver. However, if the SONET Framer/ASIC is synchronized to
a separate crystal, the XRT91L81 has two output clock references that can be used to synchronize the SONET
Framer/ASIC. TXPCLKOP/N is a 622/666MHz LVDS output clock source that is derived from the input clock
reference of the transceiver. TXCLKO16P/N is a 155.52/166MHz LVDS auxillary output clock source that is
also derived from the input clock reference. Either of these two output clock sources can be used to
synchronize the SONET Framer/ASIC to the XRT91L81. If the auxillary clock source is not used, it can be tri-
stated by pulling TRIRXCLKO16 "High". A simplified block diagram of the parallel interface is shown in
Figure 7.
FIGURE 7. TRANSMIT PARALLEL INPUT INTERFACE BLOCK
SONET Framer/ASIC
TXDI0P/N
TXDI1P/N
TXDI2P/N
TXDI3P/N
TXCLKIP/N
TXPCLKOP/N
XRT91L81 OC48
Transceiver
16
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