Z8622912PSC View Datasheet(PDF) - Zilog
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Description
MFG CO.
'Z8622912PSC' PDF : 52 Pages View PDF
ZiLOG
Table 14. XDS Display Commands*
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Note: *Changing the ON/OFF state of the 16-Second Erase
Timer has no affect on the current display mode in operation.
Read And Write Commands
Read Selects. There are two Read Select commands
(RDS1 and RDS2) in the Z86229. Each command is one
byte in size and indicates that a read should take place.
RDS1 specifies that one byte is read from the Z86229; like-
wise, RDS2 indicates that two bytes are read.
RDS1 = 40h–47h. RDS1 is a one-byte command used to
initiate a one-byte read sequence. This action is performed
by moving the contents of the register identified by the ad-
dress field (AD00:02) of the command to the output register.
Addresses 0h–7h are valid in the RDS1 command field
AD00:02.
Bit CM7 CM6 CM5
0
1
0
W
W
W
CM4 CM3 CM2 CM1 CM0
0 AD03 AD02 AD01 AD00
WW W WW
Figure 13. RDS1–Read One Byte
(RDS1 = 40h–47h)
RDS2 = 60h–66h. RDS2 is a one-byte command which is
used to initiate a two-byte read sequence. This action is per-
formed by moving the contents of the two consecutive reg-
isters, starting with the one identified by the address portion
of the command (AD00:AD02), to the output registers, set-
ting the RD2 bit in the SS register. Only Addresses 0h–6h
are valid in the RDS2 command field AD00:02.
Bit 7
6
5
4
3
2
1
0
0
1
1
0
0 AD02 AD01 AD00
W WW W W W WW
Figure 14. RSD2–Read Two Bytes
(RDS2 = 60h–66h)
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Note: For XDS data recovery, when the XDS Filter Register
(see Internal Register section) is enabled for the packets,
the Z86229 automatically establishes the two-byte recov-
ery mode, moving the recovered data bytes to the output
register.
Reading Data From The Z86229
READ1 = F8h. This command reads one byte in the SPI mode.
READ2 = F9h. This command reads two bytes in the SPI mode.
Bit 7
1
W
6
5
4
32
1
0
1
1
1
10
0 RD2
W W WW W WW
Figure 15. READx–Read x Bytes
(READ1/2 = F8h/F9h)
The READx commands do not affect the status of the RDY
bit in the Serial Status (SS) register, and can be executed
independent of the RDY status.
In both serial communications modes, the DAV bit in the
SS register indicates when the data is available. When the
RD2 bit is Low, the DAV is cleared on the rising edge of
SCK at the LSB of the first data byte. When the RD2 bit is
High, the DAV is cleared on the rising edge of SCK at the
LSB of the second data byte. The RD2 bit is only valid if
the DAV is High.
Reading in the I2C mode is selected by the R/NW bit in the
Slave Address byte. The first byte after the Slave Address
byte is SS followed by the data in output buffers (A and B,
respectively). If the instruction being executed is a one-byte
read, then buffer A contains the read data and buffer B con-
tains all ones.
Writing to the Z86229
WRxx = C0h–DFh
Bit 7
6
5
4
3
2
1
0
1
1
0
0
0 AD02 AD01 AD00
W W W WW W WW
Figure 16. WRxx–Write Register xx
(WRx = C0h–DFh)
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