Z8622912PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z8622912PSC' PDF : 52 Pages View PDF
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INTERNAL REGISTERS
Information controlling the setup and operation of the
Z86229 are maintained in several registers. The user may
read or alter the contents of these registers as required.
Serial Status (SS) Register Address = Not Required
Bit D7 D6 D5 D4 D3 D2 D1 D0
RDY DAV RD2 WOVR INTR ROVR FLD LOCK
R
RR
RR
R
R
R
Figure 18. Serial Status Register
(Address not required)
D0–LOCK. Active High, indicating that the internal sync
circuits are locked. This bit may be used as an indication
of the presence of a video signal.
D1–FLD. This bit signals the current video field. Low =
Field 2, High = Field 1.
D2–ROVR. Active High, indicating that the data available
in the output buffer has not been read out and, new data has
been written over it.
D3–INTR. Active High, indicating that an interrupt other
than DAV is pending.
D4–WOVR. Active High, indicating a serial input data over-
run has occurred.
D5–RD2. Signals the number of bytes available for output.
Low = 1 byte, High = 2 bytes.
D6–DAV. Active High, indicating that data is available to
be read out.
D7–RDY. Active High, indicating that the port input buffer
is empty. Only the NOP, RESET, and READ instructions
may be sent if RDY is Low.
Configuration Register Address = 00h
Bit D7 D6
D5
D4
D3
D2
D1
D0
res res res res VLK HLK MONO TVS
R/W R/W R/W R/W
Figure 19. Configuration Register (Address = 00h)
D0–TVS. This bit selects the television standard. High se-
lects PAL and Low selects NTSC. The default is NTSC.
When PAL is selected, the display defaults to 15 TV scan
lines per display row.
D1–MONO. This bit selects monochrome operation. Active
High indicates that the character luminance is output on all
three color pins (RGB). The default is Low, selecting COL-
OR operation.
D2–HLK. This bit selects the horizontal signal source to be
used to lock the VCO (Low = Internal, High = HIN). The
default is Internal.
D3–VLK. This bit selects the vertical signal source to be used
to establish a vertical sync lock (Low = Internal, High =
VIN). The default is Internal. When the Internal lock is en-
abled, the VIN/INTRO pin defaults to the INTRO output
mode. Interrupts should not be selected in the Interrupt
Mask register if the VLK mode is used.
D4–D7. Reserved.
Display Register Address = 01h
Bit D7
D6 D5 D4 D3 D2 D1
D0
O15 ODRP CENH C15 CDRP TENH T15 TDRP
R/W R/W R/W R/W R/W R/W R/W R/W
Figure 20. Display Register (Address = 01h)
D0–TDRP. This bit selects Drop Shadow or Full Box in Text
mode (High = DROP SHADOW and Low = BOX). The de-
fault is Low.
D1–T15. This bit selects the number of TV lines per char-
acter row in a Text display (High = 15 lines/row and Low
= 13 lines/row). The default is Low.
D2–TENH. This bit enables Enhanced Attributes for a Text
display (High = Disabled, Low = Enabled). The default is
Low.
D3–CDRP. This bit selects Drop Shadow or Full Box in
CAPTION mode (High = DROP SHADOW and Low =
BOX). The default is Low.
D4–C15. This bit selects the number of TV lines per char-
acter row in a CAPTION display (High = 15 lines/row and
Low = 13 lines/row). The default is Low.
D5–CENH. This bit enables Enhanced Attributes for a CAP-
TION display (High = Disabled, Low = Enabled). The de-
fault is Low.
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