Z86E7216PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E7216PSC' PDF : 74 Pages View PDF
Z86E72/E73
OTP IR Microcontrollers
After the POR time, /RESET is a Schmitt-triggered input. During the reset cycle, /DS is held active Low while /AS cy-
To avoid asynchronous and noisy reset problems, the cles at a rate of TpC/2. Program execution begins at loca-
1 Z86L7X is equipped with a reset filter of four external tion 000CH, 5-10 TpC cycles after the RST is released. For
clocks (4TpC). If the external reset signal is less than 4TpC Power-On Reset, the typical reset output time is 5 ms. The
in duration, no reset occurs. On the fifth clock after the re- Z86E7X devices do not have internal pull resistors on
set is detected, an internal RST signal is latched and held Port 3 inputs.
for an internal register count of 18 external clocks, or for
the duration of the external reset, whichever is longer.
P31 (AN1)
PREF1
Z86LXX
MCU
Pref1
P31
P32
P33 Port 3
(I/O or Handshake)
P34
P35
P36
P37
200 KΩ
Mask
Option
Note:
P31, 32, 33 have a 200 KΩ
mask option called Mask
option 3 similar to Mask
options 1 and 2.
R247 = P3M
D1
1 = Analog
0 = Digital
DIG.
+
COMP1
AN.
-
IRQ2, P31 Data Latch
P32 (AN2)
P33 (REF2)
+
COMP2
-
IRQ0, P32 Data Latch
From Stop-Mode
Recovery Source
IRQ1, P33 Data Latch
Figure 18. Port 3 Configuration
DS96LVO1100
PRELIMINARY
1-25
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