Z86L7808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86L7808PSC' PDF : 59 Pages View PDF
Zilog
Z86L78
IR/Low-Voltage Microcontroller
HALT. HALT turns off the internal CPU clock, but not the Port Configuration Register (PCON). The PCON regis-
XTAL oscillation. The counter/timers and external inter- ter configures the comparator output on Port 3. It is locat-
rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.
The devices are recovered by interrupts, either externally
ed in the expanded register file at Bank F, location 00 (Fig-
ure 32).
1
or internally generated. An interrupt request must be exe-
cuted (enabled) to exit HALT Mode. After the interrupt ser-
vice routine, the program continues from the instruction af-
PCON (FH) 00H
ter the HALT.
D7 D6 D5 D4 D3 D2 D1 D0
STOP. This instruction turns off the internal clock and ex-
ternal crystal oscillation and reduces the standby current
to 10 µA (typical) or less. STOP Mode is terminated only
by a reset, such as WDT time-out, POR, SMR, or external
reset. This causes the processor to restart the application
program at address 000CH.
* Default Setting After Reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
In order to enter STOP (or HALT) Mode, it is necessary to
first flush the instruction pipeline to avoid suspending exe-
cution in mid-instruction. To do this, the user must execute
a NOP (opcode = FFH) immediately before the appropriate
SLEEP instruction, i.e.,
FF NOP
6F STOP
FF NOP
7F HALT
; clear the pipeline
; enter STOP Mode
or
; clear the pipeline
; enter HALT Mode
Figure 32. Port Configuration Register (PCON)
(Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the com-
parator used in Port 3. A 1 in this location brings the com-
parator outputs to P34 and P37, and a 0 releases the Port
to its standard I/O configuration.
DS97LVO0701
2-41
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