Z86L7808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86L7808PSC' PDF : 59 Pages View PDF
Zilog
Z86L78
IR/Low-Voltage Microcontroller
WDT Time Select (D0, D1). Selects the WDT time period. WDTMR During HALT (D2). This bit determines whether
It is configured as shown in Table 6.
or not the WDT is active during HALT Mode. A 1 indicates
Table 6. WDT TIme Select
active during HALT. The default is 1.
1
WDTMR During STOP (D3). This bit determines whether
Time-Out of
or not the WDT is active during STOP Mode. Since the
Internal RC Time-Out of
XTAL clock is stopped during STOP Mode, the on-board
D1
D0
OSC
XTAL Clock
RC has to be selected as the clock source to the
0
0
5 ms min
256 TpC
WDT/POR counter. A 1 indicates active during STOP. The
0
1
10 ms min
512 TpC
default is 1.
1
0
20 ms min
1
1
80 ms min
Notes:
TpC = XTAL clock cycle
The default on reset is 10 ms
1024 TpC
4096 TpC
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0, which selects the RC oscillator.
/RESET
5 Clock
Filter
* CLR 2
CLK
18 Clock RESET
Generator
RESET
CK Source
Select
(WDTMR)
XTAL
VDD
VBO/VLV
2V REF.
M
U
INTERNAL
X
RC
OSC.
Low Operating
+ Voltage Det.
-
WDT TAP SELECT
POR WDT1 2
3
4
CLK *CLR1 WDT/POR Counter Chain
WDT
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR)
* /CLR1 and /CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low to High input translation.
DS97LVO0701
Figure 38. Resets and WDT
Internal
RESET
Active
High
2-47
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