Z86L7808PSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86L7808PSC' PDF : 59 Pages View PDF
Z86L78
IR/Low-Voltage Microcontroller
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be en-
abled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.
Zilog
The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the
time-out period. Bit 2 determines whether the WDT is ac-
tive during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 38). This reg-
ister is accessible only during the first 64 processor cycles
(128 XTAL clocks) from the execution of the first instruc-
tion after Power-On-Reset, Watch-Dog Reset, or a Stop-
Mode Recovery (Figure 35). After this point, the register
cannot be modified by any means, intentional or other-
wise. The WDTMR cannot be read and is located in Bank
F of the Expanded Register Group at address location
0FH. It is organized as follows:
WDTMR (0F) F
D7 D6 D5 D4 D3 D2 D1 D0
* Default Setting After Reset
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
Figure 37. Watch-Dog TImer Mode Register
(Write Only)
2-46
DS97LVO0701
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