5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
Link Ports: 2 × CLK Speed Operation
Parameter
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
tLCLKRWL
tLCLKRWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (2 × Operation)
LCLK Width Low
LCLK Width High
5V
Min
Max
2.5
2.25
tCK/2
4.5
4.25
3.3 V
Min
Max
2.25
2.25
tCK/2
5
4
Units
ns
ns
ns
ns
ns
Switching Characteristics:
tDLAHC
tDLALC
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High1
18 + DT/2 29.5 + DT/2
6
16.5
18 + DT/2 30.5 + DT/2
ns
6
18.5
ns
Transmit
Timing Requirements:
tSLACH
LACK Setup Before LCLK High
19
19
ns
tHLACH
LACK Hold After LCLK High
–6.75
–6.5
ns
Switching Characteristics:
tDLCLK
tDLDCH
tHLDCH
tLCLKTWL
tLCLKTWH
tDLACLK
LCLK Delay After CLKIN
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
–2
(tCK/4) – 1
(tCK/4) – 1
(tCK/4) + 9
9
3
(tCK/4) + 1
(tCK/4) + 1
(3 × tCL/4) + 17
9
ns
2.75
ns
–2
ns
(tCK/4) – 0.75 (tCK/4) + 1.5
ns
(tCK/4) – 1.5 (tCK/4) + 1
ns
(tCK/4) + 9
(3 × tCL/4) + 17 ns
NOTE
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
REV. A
–31–
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