5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
(per data line). The hold time will be tDECAY plus the minimum
16.0
disable time (i.e., tHDWD for the write cycle).
14.0
14.7
REFERENCE
SIGNAL
12.0
RISE TIME
10.0
tDIS
VOH (MEASURED)
VOL (MEASURED)
tMEASURED
tENA
VOH (MEASURED) – ∆V
VOL (MEASURED) + ∆V
tDECAY
2.0V
1.0V
VOH (MEASURED)
VOL (MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 27. Output Enable/Disable
IOL
TO
OUTPUT
PIN
50pF
+1.5V
IOH
Figure 28. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
INPUT OR
OUTPUT
1.5V
1.5V
8.0
7.4
FALL TIME
6.0
4.0
3.7
2.0
1.1
00
20 40 60 80 100 120 140 160 180 200
LOAD CAPACITANCE – pF
Figure 30. Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 5 V)
3.5
3.0
2.9
2.5
RISE TIME
2.0
1.6
1.5
FALL TIME
1.0
0.6
0.5
0
0 20 40 60 80 100 120 140 160 180 200
LOAD CAPACITANCE – pF
Figure 31. Typical Output Rise Time (0.8 V –2.0 V)
vs. Load Capacitance (VDD = 5 V)
Figure 29. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 28). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 30 and 31
show how output rise time varies with capacitance. Figure 32
graphically shows how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see the previous section Output Disable
Time under Test Conditions.) The graphs of Figures 30, 31 and
32 may not be linear outside the ranges shown.
5
4.5
4
3
2
1
NOMINAL
–0.7
–1
25
50
75
100
125
150 175
200
LOAD CAPACITANCE – pF
Figure 32. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature) (VDD = 5 V)
–38–
REV. A
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