5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
JTAG Test Access Port and Emulation
Parameter
Timing Requirements:
tTCK
TCK Period
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low1
System Inputs Hold After TCK Low1
TRST Pulsewidth
5V
Min
Max
tCK
5
6
8
18.5
4tCK
3.3 V
Min
Max
tCK
5
6
8
19
4tCK
Units
ns
ns
ns
ns
ns
ns
Switching Characteristics:
tDTDO
tDSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low 2
13
13
ns
20
20
ns
NOTES
1System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, RPBA, IRQ2-0, FLAG2-0, DR0, DR1, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
2System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG2-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT 3-0, LxCLK, LxACK, BMS.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tSTAP
tDTDO
tDSYS
tTCK
tHTAP
tSSYS
tHSYS
Figure 25. IEEE 11499.1 JTAG Test Access Port
–36–
REV. A
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