ACS8509 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8509' PDF : 68 Pages View PDF
ACS8509 SETS
ADVANCED COMMUNICATIONS
Register Map Description
FINAL
DATASHEET
Table 14 Register Description
Addr.
(Hex)
Register Name
chip_id
Description
This register contains the chip ID.
00
Bits (7:0) Chip ID bits (7:0).
01
02 chip_revision
03 cnfg_control1
Bits (7:0) Chip ID bits (15:8).
This read only register contains the chip revision number.
This revision = 1
Last revision (engineering samples) = 0.
Bits (7:6) Unused.
Default Value (Bin)
00111110
00100001
00000001
Bit 5
=1 32/24 MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal
77.76 MHz. Thus the normal OC-3/STM1 outputs are replaced with multiple E1/T1
rates. Note: Dig2 set bits (Reg. 39h Bits (7:6)) must be set to 11 for this mode.
=0 77.76MHz to APLL.
Bit 4
=1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL
section such that their phases align. This is necessary in order to have phase
alignment between inputs and output clocks at OC-3 derived rates (6.48 MHz to
77.76 MHz). Keeping this bit high may be necessary to avoid the dividers getting out
of synchronization when quick changes in frequency occur such as a force into
Free-run.
=0 The dividers may get out of phase following step changes in frequency, but in this
mode the correct number of high frequency edges is guaranteed within any
synchronization period. The output will frequency lock (default).
The device will always remain in synchronization 2 seconds from a reset, before the
default setting applies.
XX000000
Bit 3
Test control - leave unchanged, or set to 0.
Bit 2
=1 When in 8k locking mode the system will lock to the rising input clock edge.
=0 When in 8k locking mode the system will lock to the falling input clock edge.
04 cnfg_control2
Bits (1:0) Test controls - leave unchanged, or set to 00.
Bits (7:6) Unused.
Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds
to approximately 140°. A lower value sets a corresponding lower phase limit. The flag
limit determines the value at which the DPLL indicates phase lost as a result of input
jitter, a phase jump, or a frequency jump on the input.
XX100010
Bits (2:0) Test controls - leave unchanged, or set to 010.
Revision 2.00/January 2006 © Semtech Corp.
Page 23
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