ACS8509 SETS
ADVANCED COMMUNICATIONS
Table 14 Register Description (cont...)
FINAL
DATASHEET
Addr.
(Hex)
Register Name
cnfg_ref_source_
frequency
Description
Default Value (Bin)
This register is used to set up each of the 4 input reference sources.
Bits (7:6) of each byte defines the operation undertaken on the input frequency, in
accordance with the following key:
00 The input frequency is fed directly into the DPLL. (default).
01 The input frequency is internally divided down to 8 kHz, before being fed into
the DPLL. (For high jitter tolerance).
10 Unsupported configuration - do not use.
11 Uses the division coefficient stored in registers 46 and 47 (cnfg_freq_divn) to
divide the input by this value prior to being fed into the DPLL. The frequency
monitors must be disabled. The divided down frequency should equal 8 kHz.
The frequency (3:0) should be set to the nearest spot frequency just below the
actual input frequency. The DivN feature works for input frequencies between
1.544 MHz and 100 MHz.
Bits (5:4) define which leaky bucket group (0-3) is used, as defined in registers 50 to
5F. (default 00).
Bits (3:0) defines the frequency of the reference source in accordance with the
following:
0000 8 kHz,
0001 1.544 MHz (SONET)/2.048 MHz (SDH) (as defined by register 34, bit 2)
(default SEC4),
0010 6.48 MHz (default <SEC3> when MSTSLVB = 1),
0011 19.44 MHz (default <SEC3> when MSTSLVB=0, and <SEC1> <SEC2>),
0100 25.92 MHz,
0101 38.88 MHz,
0110 51.84 MHz,
0111 77.76 MHz,
1000 155.52 MHz,
1001 2 kHz,
1010 4 kHz.
26
Frequency of reference source <SEC1>.
00000011
27
Frequency of reference source <SEC2>.
00000011
2A
Frequency of reference source <SEC3>.
00000010
(MSTSLVB=0)
00000011
(MSTSLVB=1)
2C
Frequency of reference source <SEC4>.
00000001
Revision 2.00/January 2006 © Semtech Corp.
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