ACS8509 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8509' PDF : 68 Pages View PDF
ACS8509 SETS
ADVANCED COMMUNICATIONS
Table 14 Register Description (cont...)
FINAL
DATASHEET
Addr.
(Hex)
Register Name
sts_priority_table
Description
This is a 16-bit read-only register.
Default Value (Bin)
Bits (15:12) Third highest priority valid source: this is the channel number of the input
reference source which is valid and has the next-highest priority to the second-
highest-priority valid source.
Bits (11:8) Second highest priority valid source: this is the channel number of the
input reference source which is valid and has the next-highest priority to the highest-
priority valid source.
Bits (7:4) Highest priority valid source: this is the channel number of the input
reference source which is valid and has the highest priority - it may not be the same
as the currently selected reference source (due to failure history or changes in
programmed priority).
Bits (3:0) Currently selected reference source: this is the channel number of the
input reference source which is currently input to DPLL.
0A
0B
sts_curr_inc_offset
0C
0D
07
sts_sources_valid
0E
0F
Note that these registers are updated by the state machine in response to the
contents of the cnfg_ref_selection_priority register and the ongoing status of
individual channels; channel number “0000”, appearing in any of these registers,
indicates that no channel is available for that priority.
Bits (7:4) Highest priority valid source (sts_priority_table bits (7:4))
Bits (3:0) Currently selected reference source (sts_priority_table bits (3:0))
Bits (7:4) 3rd-highest priority valid source (sts_priority_table bits (15:12))
Bits (3:0) 2nd-highest priority valid source (sts_priority_table bits (11:8))
This read-only register contains a signed-integer value representing the 19 significant
bits of the current increment offset of the digital PLL. The register may be read
periodically to build up a historical database for later use during holdover periods
(this would only be necessary if an external oscillator which did not meet the stability
criteria described in Local Oscillator Clock section is used). The register will read
00000000 immediately after reset.
Bits (7:0) sts_curr_inc_offset bits (7:0)
Bits (7:0) sts_curr_inc_offset bits (15:8)
Bits (7:3) Unused
Bits (2:0) sts_curr_inc_offset bits (18:16)
This register contains a bit to show validity for every reference source.
=1 Valid source
=0 Invalid source (default)
Bit 7
SEC2
Bit 6
SEC1
Bits (5:0) Unused
Bits (7:5)
Bit 4
Bit 3
Bit 2
Bits (1:0)
Unused
SEC4
Unused
SEC3
Unused
0000000
0000000
00000000
00000000
XXXXX000
00000000
XX000000
Revision 2.00/January 2006 © Semtech Corp.
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