ACS8510 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8510' PDF : 69 Pages View PDF
ACS8510 Rev2.1 SETS
ADVANCED COMMUNICATIONS
Register Map Description
FINAL
Table 12. Register Map Description
Addr. Parameter Name
(Hex)
Description
chip_id
This register contains the chip ID = 8510 (decimal)
00
Bits (7:0) Chip ID bits (7:0)
01
chip_revision
02
cnfg_control1
Bits (7:0) Chip ID bits (15:8)
This read only register contains the chip revision number
This revision = 1
Last revision (engineering samples) = 0
Bits (7:6) Unused
Default
Value (bin)
00111110
00100001
00000001
Bit 5
=1 32/24MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76Mhz.
Thus the normal OC3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits
(Reg. 39h Bits (7:6)) must be set to 11 for this mode.
=0 77.76MHz to APLL
Bit 4
=1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section
such that their phases align. This is necessary in order to have phase alignment between inputs
and output clocks at OC3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be
necessary to avoid the dividers getting out of synchronization when quick changes in frequency
03
occur such as a force into Free-Run.
XX000000
=0 The dividers may get out of phase following step changes in frequency, but in this mode the
correct number of high frequency edges is guarenteed within any synchronization period. The
output will frequency lock (default).
The device will always remain in synchronization 2 seconds from a reset, before the default
setting applies.
Bits 3
Test control - leave unchanged, or set to '0'
Bit 2
=1 When in 8k locking mode the system will lock to the rising input clock edge.
=0 When in 8k locking mode the system will lock to the falling input clock edge.
cnfg_control2
Bits (1:0) Test controls - leave unchanged, or set to '00'
Bits (7:6) Unused
Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds to
04
approximately 140°. A lower value sets a corresponding lower phase limit. The flag limit
determines the value at which the DPLL indicates phase lost as a result of input jitter, a phase
XX100010
jump, or a frequency jump on the input
sts_interrupts
Bits (2:0) Test controls - leave unchanged, or set to '010'
This register contains one bit for each bit of sts_sources_valid, one for loss of reference the
device was locked to, and another for the operating mode. All bits are active high.
All bits except the main_ref_failed bit (bit 14) are set on a 'change' in the state of the relevent
status bit, i.e. if a source becomes valid, or goes invalid it will trigger an interrupt. If the
Operating Mode (register 9) changes state the interrupt will be generated.
Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference
that the device is locked to more quickly than the activity monitors can support. If bit 6 of the
cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the
TDO pin of the device.
All bits are maskable by the bits in the cnfg_interrupt_mask register. Each bit may be cleared
individually by writing a '1' to that bit, thus resetting the interrupt. Any number of bits can be
cleared with a single write operation. Writing '0's will have no effect.
05
Bits (7:0) <I_8> to <I_1>
00000000
06
Bits (7:0) Operating mode, main ref failed, <I_14> to <I_9>
00000000
Revision 2.00/September 2003 Semtech Corp.
27
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