ACS8514T View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

ACS8514T

Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender

Semtech Corporation 

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ACS8514 SETS Buddy

ADVANCED COMMS & SENSING FINAL

DATASHEET

Both the monitor DPLL and the T4 DPLL can be used as a

frequency meter. The frequency value measured and

reported by the DPLLs corresponds to the integral path

value in the DPLLs. As such it is a filtered version of the

actual input frequency. The time constant of the filtering is

inversely proportional to the DPLL bandwidth. The value is

a 19-bit signed number with one LSB representing

0.0003068 ppm (range of ±80 ppm). Reading this

regularly can show how the currently locked source is

varying in value e.g. due to frequency wander on its input.

Frequency Averagers

Modes are included to provide additional internal filtering

on the frequency value from the monitor DPLL. It would

also be possible to combine the internal averaging filters

with some additional software filtering. For example, the

internal fast filter could be used as an anti-aliasing filter

and the software could further filter this before

determining the actual average frequency. To support this

feature, a facility to read out the internally averaged

frequency has been provided. By setting register 40h, bit

5, the value read back from the cnfg_average_frequency

register (register 3E, 3F, 40) will be the filtered value.

The amount of filtering applied is set by register 40h, bits

6 & 7 and gives additional filter poles of 8 minutes or 110

minutes.

An Example:

Select fast holdover averaging mode by setting register

40h bits 6 & 7 high.

Select to be able to read back filtered output by setting

register 40h bit 5 high.

Software reads averaged value from the cnfg_average_

frequency register at address 3Eh, 3Fh & 40h. All bytes of

a multi-byte value such as this are frozen internally until

all bytes have been read, or until the same byte is read

again, in order to correctly build up the multi byte word.

Phase Monitoring

The T4 DPLL will be monitoring the phase of its selected

source with respect to its own output and frequency with

respect to a calibrated (see register 3Ch, 3Dh) version of

the external 12.8 MHz TCXO.

When register 65h, bit 7 is set to ‘1’ the phase detector

from T4 DPLL is used to measure the phase between the

selected input for the T4 DPLL (set either by priorities in

registers 18h to 1Eh or register 35h, bits 3:0) and the

selected input for the monitor DPLL (set by register 33).

The T4 DPLL outputs are then invalid since the PLL

feedback loop is removed.

The monitor DPLL will also be monitoring the phase of its

selected source with respect to its own internal output and

frequency with respect to a calibrated (see register 3Ch,

3Dh) version of the external 12.8 MHz TCXO. The input

phase, as seen at the DPLL phase detector, can be read

back from register 77h and 78h. The reporting of the

monitor DPLL or T4 DPLL phase detector value is

controlled by register 4Bh, bit 4. One LSB corresponds to

approximately 0.7 degrees phase difference.

The phase between two inputs may be measured by by the

monitor DPLL by switching from source A to source B and

recording the measured phase, first at source A (which will

be near to zero if the PLL has had time to pull in) and then

at source B. Measuring the phase value 30 ms after

source B is selected allows enough time for an average

phase measurement to be made and reported to register

77h & 78h, but it is before the DPLL loop has had time to

pull in the phase back to zero. It is beneficial to set the

DPLL bandwidth to the lowest value (e.g. 0.1 Hz when

TCXOs used or down to 0.5 mHz with sufficiently stable

OCXOs) to slow the rate of this pull-in.

An averaging filter is used in the phase measurement

block to get an accurate value. The bandwidth of this filter

is 100 Hz (when DPLL bandwidth at 0.5m Hz to 35 Hz) or

200 Hz (when DPLL bandwidth at 70 Hz). Hence around

30 ms is enough for a settled phase value, although this

will depend on the magnitude of the phase change.

Using the above method a phase measurement could be

made between the most accurate clock source in a

system, which would be from an ACS8530 clock output,

and any other input clock, such that TIE, MTIE and TDEV

could be subsequently calculated by software.

Alternatively the frequency of a selected source could be

monitored with respect to the external TCXO/OCXO, as a

way of deriving the TIE, MTIE and TDEV result. It may be

that the external OCXO is the most stable reference in a

system and therefore the most appropriate for input

comparisons. A higher monitor DPLL bandwidth of, for

example 8 Hz, would allow input wander to be measured,

separate from input jitter which would be filtered out

according to the setting of the DPLL bandwidth. The

frequency accuracy of 0.0003ppm corresponds to a rate

of change of phase accuracy of 0.3 ns per second.

The monitor DPLL could be used for accurate analysis of

the standby clock sources and the T4 DPLL left to provide

the additional T4 path in a system.

Revision 3.00 April 2007 © Semtech Corp.

Page 13

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