ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ADVANCED COMMS & SENSING FINAL
Figure 4 Measured Jitter Transfer Characteristics T4 DPLL
ACS8514 SETS Buddy
DATASHEET
Replication of Status & Priority Tables
The ACS8514 is designed to partner an ACS8520 or ACS8530.
As such there is a need to duplicate the input source
quality information and input priorities. A similar need also
arises in a redundant system where a slave system
shadows a master system.
All devices can independently monitor their reference
sources and determine the validity of each source. A facility
to make it easier to share the input validity information is
provided in the ACS8514, in the form of the
cnfg_sts_remote_sources_valid register (registers 30 &
31). If one device reports an invalid channel, the same
channel can be made invalid in another device by writing a
zero to the relevant position in register 30 or 31.
Register sts_sources_valid (address 0E & 0F) reports a
summary of the input status for each channel. This
information can then be written to the cnfg_sts_remote_
sources_valid register of the other device. This will ensure
that any input source considered invalid by one device is
also considered invalid by the other.
T4 Generation in Master and Slave ACS8514
As specified by the I.T.U., there is no need to align the
phases of the T4 outputs in Master and Slave devices. For
a fully redundant system, there is a need, however, to
ensure that all devices select the same reference source.
As there is no need to guarantee the alignment of phase of
the T4 outputs, the Slave devices T4 input does not need
to lock to the Masters T4 output, but only needs to ensure
that it locks to the same external reference source. There
is no defined Holdover requirement for the T4 path.
Output Clock Ports
The device supports outputs from the T4 DPLL in CMOS
(TTL compatible) or AMI composite clock format.
TO1 is a CMOS direct digitally synthesized output from the
T4 DPLL at E1/SDH (2.048 MHz) or DS1/SONET (1.544
MHz) rate. The output rate is set by register 64, bit 4. Since
it is digitally derived it has an output jitter of typically
0.027 UI p-p at 2.048 MHz or 0.020 UI p-p at 1.544 MHz.
This is 13 ns p-p and 3.8 ns RMS.
TO2 is an AMI format composite clock, consisting of a 64
kHz AMI clock with 8 kHz boundaries marked by deliberate
violations of the AMI coding rules, as specified in ITU
recommendation G.703[6]. Departures from the nominal
pattern are detected within the ACS8514, and may cause
reference-switching if too frequent. The jitter on the TO2
output is < 1ns p-p. See Table 29 for more output details.
The T4 outputs TO1 and TO2 can be enabled/disabled via
register 63 bits [5:4].
Table 8 Output Table
Port
Name
Output Port
Technology
TO1
TTL/CMOS
TO2
AMI
Frequencies Supported
Fixed frequency, either 1.544 MHz
or 2.048 MHz.
64/8 kHz (composite clock, 64 kHz
+ 8 kHz), fixed frequency.
Revision 3.00 April 2007 © Semtech Corp.
Page 18
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