ACS8514T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514T
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514T' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Selection of Input Reference Clock Source
The input reference sources for the T4 DPLL may be
selected automatically by an order of priority (via registers
18h to 1Eh, register 4Bh, bit4 must be set to ‘1’).
Alternatively it can be forced by external software control
(registers 35h, bits 3:0).
The phase and frequency monitor DPLL has its source
selected by external control via register 33h, bit 3:0.
Automatic operation selects a reference source based on
its pre-defined priority and its current availability. A table is
maintained which lists all reference sources in the order of
priority. This is initially defined by the default configuration
and can be changed via the microprocessor interface by
the network manager. In this way, when all the defined
sources are active and valid, the source with the highest
programmed priority is selected but, if this source fails,
the next-highest source is selected, and so on.
The T4 DPLL always operates in revertive mode such that
if a valid source has a higher priority than the currently
selected reference, a switch over will take place.
Forced Control Selection
For the T4 DPLL register 35 controls both the choice of
automatic or forced selection and the selection itself. For
automatic choice of source selection, the 4 LSB bit value
is set to all zeros. To force a particular input (I n) , the bit
value is set to n (bin).
For the monitor DPLL register 33 controls input selection
choice. The power up default has the 4 LSB bit value set
to all ones, whereby the DPLL will select the first valid
source. The register should be set to a value from 1 to 14
to select the required input for monitoring.
Automatic Control Selection
When an automatic T4 DPLL selection is required, (see
above), the priority for each input should be uniquely set
in registers 18h to 1Eh (make sure register 4B, bit 4 = 1).
Each register holds a 4-bit value which represents the
desired priority of that particular port. Unused ports should
be given the value, 0000, in the relevant register to
indicate they are not to be included in the priority table.
On power-up, or following a reset, the whole of the
configuration file will be defaulted to the values defined by
Table 5. The selection priority values are all relative to
each other, with lower-valued numbers taking higher
priorities. Each reference source should be given a unique
number; the valid values are 1 to 15 (dec). A value of zero
disables the reference source. However if two or more
inputs are given the same priority number those inputs will
be selected on a first in, first out basis. If the first of two
same priority number sources goes invalid the second will
be switched in. If the first then becomes valid again, it
becomes the second source on the first in, first out basis,
and there will not be a switch. If a third source with the
same priority number as the other two becomes valid, it
joins the priority list on the same first in, first out basis.
Modes of Operation
The T4 DPLL in the ACS8514 has three internal modes of
operation: Free-run, Locked and Holdover. Only locked or
not locked is reported in a status register (register 09,
bit6).
After power up and before any sources become qualified
and selected the T4 DPLL will either free run, generating
an output frequency to the same accuracy as the external
TCXO/OCXO or its output will be squelched, depending on
register 64h, bit 6. The accuracy of the external oscillator
can be calibrated to appear more accurate via registers
3Ch & 3Dh.
Once the T4 DPLL has locked to a source, then when that
source fails, it will hold its last output frequency or its
output will be squelched, again depending on register 64
hex, bit 6.
Since the outputs from the monitor DPLL are not accessible
its internal output frequency and operating modes are less
relevant. Indication as to whether it is locked to a source
or not are given in register 09h, bits 2:0.
Revision 3.00 April 2007 © Semtech Corp.
Page 14
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