ACS8514T View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

ACS8514T

Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender

Semtech Corporation 

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ACS8514 SETS Buddy

ADVANCED COMMS & SENSING FINAL

DATASHEET

DPLL Architecture and Configuration

A Digital PLL gives a stable and consistent level of

performance that can be easily programmed for different

dynamic behavior or operating range. It is not affected by

operating conditions or silicon process variations. Digital

synthesis is used to generate the required SONET/SDH

output frequencies. An analog PLL is used to filter the

synthesized digital clock before it is fed back to the DPLL

input. This avoids any digital sampling induced wander or

jitter.

The DPLLs in the ACS8514 are uniquely very

programmable for all PLL parameters of bandwidth (from

0.5 mHz up to 70 Hz), damping factor (from 1.2 to 20),

frequency acceptance and output range (from 0 to 80

ppm, typically 9.2 ppm) and input frequency (12 common

SONET/SDH spot frequencies). There is no requirement to

understand the loop filter equations or detailed gain

parameters since all high level factors such as overall

bandwidth can be set directly via registers in the

microprocessor interface. No external critical components

are required for either the internal DPLLs or APLLs,

providing another key advantage over traditional discrete

designs.

The T4 DPLL is similar in structure to the monitor DPLL,

but its bandwidth is limited to 18, 35 and 70 Hz.

Monitor DPLL Main Features

• Programmable DPLL bandwidth in 10 steps from

0.5 mHz to 70 Hz.

• Programmable damping factor: For optional faster

locking. Factors = 1.2, 2.5, 5, 10 or 20.

• Multiple phase lock detectors.

• Multi-cycle phase detection and locking, programmable

up to ±8192 UI (readable up to 23000° as a 16 bit

register reports the value).

• Input frequency averaging with a choice of averaging

times: 8 minutes or 110 minutes.

T4 DPLL Main Features

• E1 (2.048 MHz) or DS1(1.544 MHz) outputs.

• Programmable DPLL bandwidth in 3 steps from 18 Hz

to 70 Hz

• Programmable damping factor: For optional faster

locking and peaking control. Factors = 1.2, 2.5, 5, 10

or 20

• Multiple phase lock detectors

• Multi-cycle phase detection and locking, programmable

up to ±8192 UI - improves jitter tolerance in direct lock

mode

• Can use the phase detector in T4 DPLL to measure the

input phase difference between two inputs (+/- 0.5UI).

The following sections detail some component parts of the

DPLL.

Monitor DPLL Automatic Bandwidth Controls

In Automatic Bandwidth Selection mode (register 3Bh, bit

7), the monitor DPLL bandwidth setting is selected

automatically from the Acquisition Bandwidth or Locked

Bandwidth configurations programmed in register 69h

and 67h respectively. If this mode is not selected, the

DPLL acquires and locks using only the bandwidth set by

register 67.

Phase Detectors

A Phase and Frequency detector is used to compare input

and feedback clocks. This operates at input frequencies

up to 77.76 MHz. The whole DPLL can operate at spot

frequencies from 2 kHz up to 77.76 MHz (155.52 MHz is

internally divided down to 77.76 MHz). A common

arrangement however is to use Lock8k mode (See register

22h to 2Dh, Bit 6) where all input frequencies are divided

down to 8 kHz internally. Marginally better MTIE figures

may be possible in direct lock mode due to more regular

phase updates. This direct locking capability is one of the

unique features of the ACS8514.

A multi-phase detector (patent pending) approach is used

in order to give an infinitesimally small input phase

resolution combined with large jitter tolerance. The

following phase detectors are used:

• Phase and frequency detector (±360° or ±180°

range)

• An Early/ Late Phase detector for fine resolution

• A multi-cycle phase detector for large input jitter

tolerance (up to 8191 UI), which captures and

remembers phase differences of many cycles between

input and feedback clocks.

The phase detectors can be configured to be immune to

occasional missing input clock pulses by using nearest

edge detection (±180° capture) or the normal ±360°

phase capture range which gives frequency locking. The

device will automatically switch to nearest edge locking

when the multi-UI phase detector is not enabled and it has

detected that phase lock has been achieved. It is possible

to disable the selection of nearest edge locking via

Revision 3.00 April 2007 © Semtech Corp.

Page 15

www.semtech.com

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