ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 64
Register Name cnfg_T4_DPLL_frequency
FINAL
DATASHEET
Description
(R/W) Register to configure the T4 Default Value
DPLL and several other
parameters for the T4 path.
0000 0001
Bit 7
Bit 6
Bit 5
Auto_squelch_ AMI_op_duty
T4
Bit 4
T4_op_
SONSDH
Bit 3
Bit 2
Bit 1
T4_DPLL_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
7
6
5
4
3
[2:0]
Not used.
Auto_squelch_T4
Register bit to automatically squelch the T4 outputs
on TO8 and TO9 when the T4 inputs have failed.
AMI_op_duty
Register bit to configure whether the composite
clock output of TO8 is 50:50 or 5:8 duty cycle.
T4_op_SONSDH
Register bit to configure the BITS output on TO9 to
be either SONET or SDH frequency, only when
Reg. 35 Bit 4 = 0, otherwise this bit is ignored and
SONET/SDH selection for TO9 is controlled by
Reg. 34 Bit 2.
Default set by SONSDHB pin - same as Reg. 34 Bit
2.
Not used.
T4_DPLL_frequency
Register to configure the frequency of operation of
the DPLL in the T4 path. The frequency of the DPLL
will also affect the frequency of the T4 APLL which,
in turn, affects the frequencies available at outputs
TO1 - TO7 see Reg. 60 - Reg. 63. It is also possible
to not use the T4 DPLL at all, but use the T4 APLL to
run directly from the T0 DPLL output, see Reg. 65
(cnfg_TO_DPLL_frequency). If any frequencies are
required from the T4 APLL then the T4 DPLL should
not be squelched, as the T4 APLL input is squelched
and the T4 APLL will free run.
-
-
0
Outputs TO8 and TO9 enabled as in Reg. 63.
1
Outputs TO8 and TO9 disabled when T4 inputs fail.
0
TO8 output 50:50 duty cycle.
1
TO8 output 5:8 duty cycle.
0
TO9 output 2.048 MHz (SDH).
1
TO9 output 1.544 MHz (SONET).
-
-
000
T4 DPLL mode = squelched (clock off).
001
T4 DPLL mode = 77.76 MHz (OC-N rates), giving
T4 APLL output frequency (before dividers) =
311.04 MHz.
010
T4 DPLL mode = 12E1, giving T4 APLL output
frequency (before dividers) = 98.304 MHz.
011
T4 DPLL mode = 16E1, giving T4 APLL output
frequency (before dividers) = 131.072 MHz.
100
T4 DPLL mode = 24DS1, giving T4 APLL output
frequency (before dividers) = 148.224 MHz.
101
T4 DPLL mode = 16DS1, giving T4 APLL output
frequency (before dividers) = 98.816 MHz.
110
T4 DPLL mode = E3, giving T4 APLL output
frequency (before dividers) = 274.944 MHz.
111
T4 DPLL mode = DS3, giving T4 APLL output
frequency (before dividers) = 178.944 MHz.
Revision 3.02/October 2005 © Semtech Corp.
Page 113
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