ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 6A (cont...)
Register Name cnfg_T4_DPLL_damping
FINAL
Description
(R/W) Register to configure the
damping factor of the T4 DPLL,
along with the gain of Phase
Detector 2 in some modes.
DATASHEET
Default Value 0001 0011
Bit 7
Bit 6
Bit 5
T4_PD2_gain_alog_8k
Bit 4
Bit 3
Bit 2
Bit 1
T4_damping
Bit 0
Bit No.
Description
Bit Value Value Description
[2:0]
T4_damping
Register to configure the damping factor of the T4
DPLL. The bit values corresponds to different
damping factors, depending on the bandwidth
selected. Damping factor of 5 being the default
(011).
The Gain Peak for the Damping Factors given in the
Value Description (right) are tabulated below.
Damping Factor
Gain Peak
1.2
2.5
5
10
20
0.4 dB
0.2 dB
0.1 dB
0.06 dB
0.03 dB
T4 DPLL damping factor at the following bandwidths
frequency selections:
18 Hz 35 Hz 70 Hz
001
1.2 1.2 1.2
010
2.5 2.5 2.5
011
5
5
5
100
5
10
10
101
5
10
20
000
Not used.
110
Not used.
111
Not used.
Address (hex): 6B
Register Name cnfg_T0_DPLL_damping
Description
(R/W) Register to configure the
damping factor of the T0 DPLL,
along with the gain of the Phase
Detector 2 in some modes.
Default Value
0001 0011
Bit 7
Bit 6
Bit 5
T0_PD2_gain_alog_8k
Bit 4
Bit 3
Bit 2
Bit 1
T0_damping
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
Not used.
T0_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6D Bit 7,
cnfg_T0_DPLL_PD2_gain.
Not used.
-
-
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
-
Revision 3.02/October 2005 © Semtech Corp.
Page 117
www.semtech.com
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