ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 69
Register Name cnfg_T0_DPLL_acq_bw
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
bandwidth of the T0 DPLL, when
not phase locked to an input.
0000 1111
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
T0_DPLL_acquisition_bandwidth
Bit 0
Bit No.
Description
Bit Value Value Description
[7:4]
[3:0]
Not used.
-
-
T0_DPLL_acquisition_bandwidth
Register to configure the bandwidth of the T0 DPLL
when acquiring phase lock on an input reference.
Reg. 3B Bit 7 is used to control whether this
bandwidth is not used or automatically switched to
when not phase locked.
1000
T0 DPLL 0.1 Hz acquisition bandwidth.
1001
T0 DPLL 0.3 Hz acquisition bandwidth.
1010
T0 DPLL 0.6 Hz acquisition bandwidth.
1011
T0 DPLL 1.2 Hz acquisition bandwidth.
1100
T0 DPLL 2.5 Hz acquisition bandwidth.
1101
T0 DPLL 4 Hz acquisition bandwidth.
1110
T0 DPLL 8 Hz acquisition bandwidth.
1111
T0 DPLL 18 Hz acquisition bandwidth.
0000
T0 DPLL 35 Hz acquisition bandwidth.
0001
T0 DPLL 70 Hz acquisition bandwidth.
All other values Not used.
Address (hex): 6A
Register Name cnfg_T4_DPLL_damping
Description
(R/W) Register to configure the
damping factor of the T4 DPLL,
along with the gain of Phase
Detector 2 in some modes.
Default Value 0001 0011
Bit 7
Bit 6
Bit 5
T4_PD2_gain_alog_8k
Bit 4
Bit 3
Bit 2
Bit 1
T4_damping
Bit 0
Bit No.
Description
Bit Value Value Description
7
[6:4]
3
Not used.
T4_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6C Bit 7,
cnfg_T4_DPLL_PD2_gain.
Not used.
-
-
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
-
-
Revision 3.02/October 2005 © Semtech Corp.
Page 116
www.semtech.com
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