ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 6C (cont...)
Register Name cnfg_T4_DPLL_PD2_gain
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for the T4 DPLL.
1100 0010
Bit 7
T4_PD2_gain_
enable
Bit 6
Bit 5
T4_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
T4_PD2_gain_digital
Bit 0
Bit No.
Description
Bit Value Value Description
[6:4]
3
[2:0]
T4_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
T4_PD2_gain_enable.
Not used.
T4_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. This setting is always used if automatic gain
selection is disabled in Bit 7, T4_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
-
-
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Address (hex): 6D
Register Name cnfg_T0_DPLL_PD2_gain
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for the T0 DPLL.
1100 0010
Bit 7
T0_PD2_gain_
enable
Bit 6
Bit 5
T0_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
T0_PD2_gain_digital
Bit 0
Bit No.
Description
Bit Value Value Description
7
T0_PD2_gain_enable
[6:4]
3
T0_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
T0_PD2_gain_enable.
Not used.
0
T0 DPLL Phase Detector 2 not used.
1
T0 DPLL Phase Detector 2 gain enabled and choice
of gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
- analog feedback at 8 kHz.
-
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
-
-
Revision 3.02/October 2005 © Semtech Corp.
Page 119
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