ACS8520 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8520' PDF : 150 Pages View PDF
ACS8520 SETS
ADVANCED COMMUNICATIONS
Address (hex): 6D (cont...)
Register Name cnfg_T0_DPLL_PD2_gain
FINAL
DATASHEET
Description
(R/W) Register to configure the Default Value
gain of Phase Detector 2 in some
modes for the T0 DPLL.
1100 0010
Bit 7
T0_PD2_gain_
enable
Bit 6
Bit 5
T0_PD2_gain_alog
Bit 4
Bit 3
Bit 2
Bit 1
T0_PD2_gain_digital
Bit 0
Bit No.
Description
Bit Value Value Description
[2:0]
T0_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. This setting is always used if automatic gain
selection is disabled in Bit 7, T0_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
Address (hex): 70
Register Name cnfg_phase_offset
[7:0]
Description
(R/W) Bits [7:0] of the phase
offset control register.
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
phase_offset_value[7:0]
Bit 2
Bit 1
Bit 0
Bit No.
Description
Bit Value Value Description
[7:0]
phase_offset_value[7:0]
Register forming part of the phase offset control.
-
See Reg. 71, cnfg_phase_offset[15:8] for more
details.
Revision 3.02/October 2005 © Semtech Corp.
Page 120
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