ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 64
Register Name cnfg_DPLL2_frequency
FINAL
Description
(R/W) Register to configure
DPLL2 Frequency.
DATASHEET
Default Value 0000 0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
DPLL2_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
[7:4]
[2:0]
Not used.
DPLL2_frequency
Register to configure the frequency of operation of
DPLL2. The frequency of DPLL2 will also affect the
frequency of the APLL2 which, in turn, affects the
frequencies available at outputs O1 and O2 see
Reg. 61 - Reg. 63. It is also possible to not use
DPLL2 at all, but use the APLL2 to run directly from
DPLL1 output, see Reg. 65
(cnfg_DPLL1_frequency). If any frequencies are
required from the APLL2 then DPLL2 should not be
squelched, as the APLL2 input is squelched and the
APLL2 will free run.
-
-
000
DPLL2 mode = squelched (clock off).
001
DPLL2 mode = 77.76 MHz (OC-N rates), giving
APLL2 frequency = 311.04 MHz.
010
DPLL2 mode = 12E1, giving APLL2 output
frequency (before dividers) = 98.304 MHz.
011
DPLL2 mode = 16E1, giving APLL2 output
frequency (before dividers) = 131.072 MHz.
100
DPLL2 mode = 24DS1, giving APLL2 output
frequency (before dividers) = 148.224 MHz.
101
DPLL2 mode = 16DS1, giving APLL2 output
frequency (before dividers) = 98.816 MHz.
110
DPLL2 mode = E3, giving APLL2 output frequency
(before dividers) = 274.944 MHz.
111
DPLL2 mode = DS3, giving APLL2 output frequency
(before dividers) = 178.944 MHz.
Address (hex): 65
Register Name cnfg_DPLL1_frequency
Description
(R/W) Register to configure
DPLL1 and several other
parameters.
Default Value 0000 0001
Bit 7
Bit 6
DPLL2_meas_ APLL2_for_
DPLL1_ph
DPLL1_E1/DS1
Bit 5
Bit 4
DPLL1_freq_to_APLL2
Bit 3
Bit 2
Bit 1
DPLL1_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
7
DPLL2_meas_DPLL1_ph
Register bit to control the feature where DPLL2 is
used to measure phase offset between the SEC
input selected by DPLL1 and either of the other two
SEC Inputs. Refer to the Section “Measuring Phase
Between Master and Slave/Stand-by SEC Sources”
on page 33.
6
APLL2_for_DPLL1_E1/DS1
Register bit to select whether the APLL2 takes its
input from DPLL2 or DPLL1. If DPLL1 is selected
then the frequency is controlled by Bits [5:4],
DPLL1_freq_to_APLL2.
0
Normal- DPLL2 normal operation.
1
DPLL2 disabled, DPLL2 phase detector used to
measure phase between selected DPLL1 input and
selected DPLL2 input.
0
APLL2 takes its input from DPLL2.
1
APLL2 takes its input from DPLL1.
Revision 3.01/August 2005 © Semtech Corp.
Page 79
www.semtech.com
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