ACS8525T View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'ACS8525T' PDF : 112 Pages View PDF
ACS8525 LC/P
ADVANCED COMMUNICATIONS
Address (hex): 65 (cont...)
Register Name cnfg_DPLL1_frequency
FINAL
Description
(R/W) Register to configure
DPLL1 and several other
parameters.
DATASHEET
Default Value 0000 0001
Bit 7
Bit 6
DPLL2_meas_ APLL2_for_
DPLL1_ph
DPLL1_E1/DS1
Bit 5
Bit 4
DPLL1_freq_to_APLL2
Bit 3
Bit 2
Bit 1
DPLL1_frequency
Bit 0
Bit No.
Description
Bit Value Value Description
[5:4]
DPLL1_freq_to_APLL2
Register to select the frequency/mode of DPLL1
which is driven to the APLL2 when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1.
Register to select DPLL1’s frequency driven to the
APLL2 (DPLL1 mode*) when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1 ; and consequently the
APLL output frequency in the T4 path.
*Note that this is not the operating frequency of
DPLL1 itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See Figure 5 “PLL Block
Diagram” on page 15.
00
DPLL1 mode = 12E1, giving APLL2 output
frequency (before dividers) = 98.304 MHz.
01
DPLL1 mode = 16E1, giving APLL2 output
frequency (before dividers) = 131.072 MHz.
10
DPLL1 mode = 24DS1, giving APLL2 output
frequency (before dividers) = 148.224 MHz.
11
DPLL1 mode = 16DS1, giving APLL2 output
frequency (before dividers) = 98.816 MHz.
3
[2:0]
Not used.
DPLL1_frequency
Register to configure the frequency driven to APLL1
(DPLL1 mode*) and consequently the APLL output
frequency in the T0 path. This register affects the
frequencies available at outputs O1 and O2, see
Reg. 61 - Reg. 63.
*Note that this is not the operating frequency of the
DPLL1 itself - which is fixed at outputting
77.76 MHz - but is the multiplied output from the LF
Output DFS block. See Figure 5 “PLL Block
Diagram” on page 15.
Note...001 is the only selection that does not
bypass APLL3. All other selections use digital
feedback.
-
-
000
DPLL1 mode = 77.76 MHz, digital feedback, APLL1
output frequency (before dividers) = 311.04 MHz.
001
DPLL1 mode = 77.76 MHz, analog feedback, APLL1
output frequency (before dividers) = 311.04 MHz.
010
DPLL1 mode = 12E1, giving APLL1 output
frequency (before dividers) = 98.304 MHz.
011
DPLL1 mode = 16E1, giving APLL1 output
frequency (before dividers) = 131.072 MHz.
100
DPLL1 mode = 24DS1, giving APLL1 output
frequency (before dividers) = 148.224 MHz.
101
DPLL1 mode = 16DS1, giving APLL1 output
frequency (before dividers) = 98.816 MHz.
110
Not used.
111
Not used.
Revision 3.01/August 2005 © Semtech Corp.
Page 80
www.semtech.com
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