AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
AD9228
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9228 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 52 shows a preferred method for clocking the AD9228. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9228 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9228,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
CLK+
0.1µF
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
50Ω 100Ω
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSM2812
CLK+
ADC
AD9228
CLK–
Figure 52. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
CLK+
CLK–
50Ω*
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515 0.1µF
PECL DRIVER
0.1µF
CLK
50Ω*
240Ω
100Ω
0.1µF
240Ω
CLK+
ADC
AD9228
CLK–
*50Ω RESISTORS ARE OPTIONAL
Figure 53. Differential PECL Sample Clock
CLK+
CLK–
50Ω*
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515 0.1µF
LVDS DRIVER
0.1µF
CLK
50Ω*
100Ω
0.1µF
CLK+
ADC
AD9228
CLK–
*50Ω RESISTORS ARE OPTIONAL
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 55). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
CLK+
0.1µF
50Ω*
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
CMOS DRIVER
OPTIONAL
100Ω
CLK+
0.1µF ADC
CLK
AD9228
0.1µF
39kΩ
CLK–
*50Ω RESISTOR IS OPTIONAL
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
CLK+
0.1µF
50Ω*
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
CMOS DRIVER
OPTIONAL
100Ω
CLK+
0.1µF ADC
CLK
AD9228
0.1µF
CLK–
*50Ω RESISTOR IS OPTIONAL
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9228 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9228. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominal. The loop has a time constant associated with
it that must be considered in applications where the clock rate
can change dynamically. This requires a wait time of 1.5 μs to
5 μs after a dynamic clock frequency increase (or decrease)
before the DCS loop is relocked to the input signal. During the
period that the loop is not locked, the DCS loop is bypassed and
the internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Rev. B | Page 22 of 52
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