AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
130
RMS CLOCK JITTER REQUIREMENT
120
110
100
16 BITS
90
80
70
10 BITS
60
50
40
30
1
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
10
100
ANALOG INPUT FREQUENCY (MHz)
14 BITS
12 BITS
1000
Figure 57. Ideal SNR vs. Input Frequency and Jitter
AD9228
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
180
360
160
340
AVDD CURRENT
140
320
120
TOTAL POWER
300
100
280
80
260
60
240
40
DRVDD CURRENT
220
20
200
0
180
10
15
20
25
30
35
40
ENCODE (MSPS)
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
250
480
460
200 AVDD CURRENT
440
TOTAL POWER
420
150
400
380
100
360
340
50
DRVDD CURRENT
320
0
300
10
20
30
40
50
60
ENCODE (MSPS)
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Rev. B | Page 23 of 52
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