AD9228 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'AD9228' PDF : 52 Pages View PDF
500
EYE: ALL BITS
ULS: 10000/15600
0
–500
–1ns
–0.5ns
0ns
0.5ns
1ns
100
50
AD9228
400
EYE: ALL BITS
200
0
ULS: 9599/15599
–200
–400
–1ns
–0.5ns
0ns
0.5ns
1ns
100
50
0
–100ps
0ps
100ps
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
ULS: 9600/15600
200
EYE: ALL BITS
0
–200
–1ns
–0.5ns
0ns
100
0.5ns
1ns
50
0
–150ps –100ps –50ps
0ps
50ps
100ps 150ps
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
(VIN + x) − (VIN − x),
Digital Output Offset Binary
Code Input Span = 2 V p-p (V) (D11 ... D0)
4095 +1.00
1111 1111 1111
2048 0.00
1000 0000 0000
2047 −0.000488
0111 1111 1111
0
−1.00
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
0
–150ps –100ps –50ps
0ps
50ps
100ps 150ps
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Rev. B | Page 25 of 52
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