ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
S/PDIF Transmitter
Serial data input to the S/PDIF transmitter can be formatted as
left-justified, I2S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter.
S/PDIF Transmitter-Serial Input Waveforms
Figure 35 shows the right-justified mode. LRCLK is high for the
left channel and low for the right channel. Data is valid on the
rising edge of serial clock. The MSB is delayed minimum in
24-bit output mode or maximum in 16-bit output mode from
an LRCLK transition, so that when there are 64 serial clock peri-
ods per LRCLK period, the LSB of the data will be right-justified
to the next LRCLK transition.
Figure 36 shows the default I2S-justified mode. LRCLK is low
for the left channel and HI for the right channel. Data is valid on
the rising edge of serial clock. The MSB is left-justified to an
LRCLK transition but with a delay.
Figure 37 shows the left-justified mode. LRCLK is high for the
left channel and LO for the right channel. Data is valid on the
rising edge of serial clock. The MSB is left-justified to an LRCLK
transition with no delay.
Table 47. S/PDIF Transmitter Right-Justified Mode
Parameter
Timing Requirement
tRJD
LRCLK to MSB Delay in Right-Justified Mode
16-Bit Word Mode
18-Bit Word Mode
20-Bit Word Mode
24-Bit Word Mode
Nominal Unit
16
SCLK
14
SCLK
12
SCLK
8
SCLK
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LSB
tRJD
LEFT/RIGHT CHANNEL
MSB MSB–1 MSB–2
Figure 35. Right-Justified Mode
Table 48. S/PDIF Transmitter I2S Mode
Parameter
Timing Requirement
tI2SD
LRCLK to MSB Delay in I2S Mode
LSB+2 LSB+1 LSB
Nominal Unit
1
SCLK
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LEFT/RIGHT CHANNEL
tI2SD
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 36. I2S-Justified Mode
Rev. B | Page 52 of 76 | March 2013
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