ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
DAI_P20–1
(TxCLK)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(SDATA)
tSITXCLKW
SAMPLE EDGE
tSITXCLK
tSISCLKW
tSISCLK
tSISFS
tSISD
tSIHFS
tSIHD
Figure 38. S/PDIF Transmitter Input Timing
Oversampling Clock (HFCLK) Switching Characteristics
The S/PDIF transmitter has an oversampling clock. This
HFCLK input is divided down to generate the biphase clock.
Table 51. Oversampling Clock (HFCLK) Switching Characteristics
Parameter
HFCLK Frequency for HFCLK = 384 × Frame Sync
HFCLK Frequency for HFCLK = 256 × Frame Sync
Frame Rate (FS)
Max
Unit
Oversampling Ratio × Frame Sync <= 1/tSIHFCLK MHz
49.2
MHz
192.0
kHz
Rev. B | Page 54 of 76 | March 2013
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