ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
ADSP-21467/ADSP-21469
SPI Interface—Master
The processor contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 53 and Table 54 applies to both.
Table 53. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
tSSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
tHSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
Switching Characteristics
tSPICLKM
tSPICHM
tSPICLM
tDDSPIDM
tHDSPIDM
tSDSCIM
tHDSM
tSPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
DPI Pin (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to DPI Pin (SPI Device Select) High
Sequential Transfer Delay
Min
8.2
2
8 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 2
4 × tPCLK – 1
Max
2.5
DPI
(OUTPUT)
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
tSDSCIM
tSPICHM
tSPICLM
tDDSPIDM
tSSPIDM
tHSPIDM
MOSI
(OUTPUT)
CPHASE = 0
tSSPIDM
MISO
(INPUT)
tHSPIDM
tDDSPIDM
tSPICLKM
tHDSPIDM
tHDSM
tSPITDM
tSSPIDM
tHSPIDM
tHDSPIDM
Figure 40. SPI Master Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 56 of 76 | March 2013
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